This invention relates generally to the field of multipliers, and more particularly to a 4-quadrant multiplier capable of operating at frequencies on the order of 400MHz.
Multipliers find a wide variety of potential uses, and are especially important in the present day art of signal processing. However, multipliers have not kept pace with the increase in operating speeds of other semiconductor devices and, as a consequence, we find many of our signal processors are limited by the operating frequencies of the multipliers used therein.
For example, consider the transversal-type adaptive equalizer shown in FIG. 1, the operation of which is well known in the prior art and will not be discussed in detail herein. The equalizer uses two sets of multipliers 10 and 12, the former acting as the weighting elements for the delay taps 14 and the latter acting as correlators for the control algorithm. It can easily be seen that the multipliers 10, 12 are an important part of the system and, although under certain conditions they can be simplified to single or two quadrant multipliers, for the purposes of this application both sets of multipliers will be assumed to be 4-quadrant multipliers.
It is often desirable to operate present day adaptive equalizers, such as that shown in FIG. 1, at frequencies from 10KHz to 10GHz. However, solid state multipliers presently available have bandwidths on the order of 70MHz and, due to the finite output impedances of semiconductor devices, the bandwidth will drop to below 10MHz when a load is added. There is, then, a need for higher frequency multipliers for use in high speed signal processing systems, such as the adaptive equalizer shown in FIG. 1.
Gain variation between individual multipliers in groups 10 and 12 will only affect the rate of convergence of the equalizer and the variation can be compensated for by using a separate error amplifier for each multiplier, rather than the single amplifier 16 shown in FIG. 1. Linearity will also only affect the rate of convergence. Therefore, gain and linearity requirements are quite flexible in the design of such high frequency multipliers.
One example of a high-speed multiplier device is discussed in U.S. Pat. No. 3,368,066. The device described therein uses field-effect transistors, operated in their triode region, as variable input resistors on either input terminal of a difference current amplifier. The drains of the FETs are tied together and each source is connected to a different amplifier input terminal. The voltage applied to the common drain terminal forms one input to the device and the voltage difference between the gate terminals forms the other input. The multiplication properties of the device are derived from the fact that, within the triode or "linear" region of operation, changes in gate voltage or drain voltage will cause proportional changes in drain current. Such a multiplier is unsatisfactory in that reversing the polarity of the drain voltage will cause the current amplifier to saturate, so that the device will only perform two-quadrant multiplication. Furthermore, although the device is referred to as a "fast" multiplier, the patentee states that it will operate at only up to 50MHz.
Another example of a prior art solid-state multiplier is given in U.S. Pat. No. 3,689,752. The multiplier described therein uses a pair of differential amplifiers in order to provide polarity discrimination. However, that device requires two amplifiers and several pairs of transistors and, in addition to having a high manufacturing cost, it will not achieve sufficiently high operating speeds.